Multicore Systems

This portal provides links to documentation about various multicore architectures.

A more informative page is the Chip Multiprocessor Watch Wiki maintained by Berkeley.




  • "IBM Power6". IBM Journal of Research and Development, 2007. (IBM link) (pdf)
  • "Power efficient processor architecture and the cell processor". H.P. Hofstee. 11th International Symposium on High-Performance Computer Architecture, 2005. (pdf) (CSLab) (IBM link)
  • "IBM Power5 chip: a dual-core multithreaded processor". R. Kalla, S. Balaram, J.M. Tendler. IEEE Micro, vol 24, no 2, pp. 40-47, Mar-Apr 2004. (pdf) (CSLab) (IBM link)


  • "Larrabee: a many-core x86 architecture for visual computing" . Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan. ACM Transactions on Graphics, 2008. (pdf) (CSLab)


  • OpenSPARC publications
  • "Niagara: a 32-way multithreaded Sparc processor". P. Kongetira, P, K. Aingaran, K. Olukotun. IEEE Micro, vol 25, no 2, pp. 21-29, Mar-Apr 2005. (pdf) (CSLab)


  • "Scheduling threads for constructive cache sharing on CMPs". S. Cheny, P. Gibbons, M. Kozuchy, V. Liaskovitis, A. Ailamaki, G. Blelloch, B. Falsafi, L. Fixy, N. Hardavellas, T. Mowry, C. Wilkerson. Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures, 2007. (pdf)


  • "Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers". J. Sampson, R. Gonzalez, J. Collard, N. Jouppi, M. Schlansker, B. Calder. Proceedings of the International Symposium on Microarchitecture, 2006. (pdf)

Speculative Execution

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Topic revision: r4 - 2008-10-08 - NikosAnastopoulos

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