Caches for Chip Multiprocessor Architectures (CMPs)

Today, there is a trend to increase the number of processors on a single chip leading to the development of chip multiprocessor (CMP), and eventually manycore, architectures. Cache design has been extensively studied in the context of uniprocessor systems and computer architects have transfered existing policies and cache design techniques from uniprocessors to the new architectures. A typical example of such a migration is the employment of the Least Recently Used (LRU) replacement policy, which is widely accepted as the best line replacement policy for uniprocessor caches. However the parameters are different in CMP systems, as the sharing of the cache hierarchy amongst several concurrent threads imposes new constraints and creates new challenges. It is important, therefore, to reevaluate the effectiveness of these policies in CMP architectures.

Prior work has investigated the interference between threads that run simultaneously on CMPs sharing different levels of the cache hierarchy and evaluated cache partitioning as a means of alleviating its consequences. A novel, low cost, cache partitioning scheme based on Bloom Filters has been proposed. This mechanism partitions the cache dynamically among the different parallel threads and achieves better performance than LRU. At the same time it shows increasing promise as the number of on-chip processors increases [SAMOS08].


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Topic revision: r2 - 2008-07-30 - KonstantinosNikas

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