Transactional Memory Bibliography Portal This portal maintains a collection of bibliography on Transactional Memories. A more extensive publication list can be found...

This portal provides links to various research papers on simultaneous multithreading. A more extensive (yet outdated) paper list can be found here: Multithreading...

Caches for Chip Multiprocessor Architectures (CMPs) Today, there is a trend to increase the number of processors on a single chip leading to the development of...

Status Conference/Workshop Submission deadline Notification Presentation Location CLOSED FAST (USENIX Conference on File and Storage Technologies...

The Compressed Sparse eXtended (CSX) format for sparse matrices is a sparse matrix format that seeks to minimize the memory footprint of the column index array of...

Distributed Processing Frameworks Large scale data management achieved by the distributed cooperation of computational and storage resources is a challenging task...

gmblock Clusters built out of commodity components are becoming more and more prevalent in the supercomputing sector as a cost effective solution for building high...

High Performance Computing The main objective of our group in this research area is to optimize critical software (mainly computationally or memory intensive applications...

High Performance Systems and Interconnects Recent advances in interconnection technologies have made clustered systems built out of commodity components an attractive...

Instruction Scheduling Related Work Links related to instruction scheduling: `Parallelizing nonnumerical code with selective scheduling and software pipelining...

The Memory Bandwidth aware Userspace Scheduler (MemBUS) Symmetric Multiprocessor (SMPs) are commonly used as the building blocks for scalable clustered systems. Often...

Multicore Systems This portal provides links to documentation about various multicore architectures. A more informative page is the Multiprocessor Watch Wiki maintained...

NoSQL Systems The increasing data volume that needs to be stored, indexed and queried for every organization (such as e mail and web logs, historical data, click streams...

SMT processors Simultaneous Multithreading (SMT) is a hardware technique that allows a conventional superscalar processor to issue instructions from multiple hardware...

For our more recent work on the Sparse Matrix Vector Multiplication check: CSX. Sparse Matrix Vector Multiplication Sparse Matrix Vector Multiplication (SPMV) is...

Stencil Computations The main objective of this activity is to optimize stencil computations for Cluster platforms with commodity (e.g. Gbit Ethernet) or sophisticated...

Transactional Memory (TM) Transactional Memory (TM) is a novel programming model for multicore architectures that allows concurrency control over multiple threads...

PDSG Research Here is the new website presenting CSLab research. Parallel, High Performance Systems We are interested in how advances in technology and architecture...

XOROS Data redundancy in DHTs is commonly accomplished through automatic replication of values to a set of close participating nodes. Such copies, once written, should...