Caches for Chip Multiprocessor Architectures (CMPs) Today, there is a trend to increase the number of processors on a single chip leading to the development of...

The Compressed Sparse eXtended (CSX) format for sparse matrices is a sparse matrix format that seeks to minimize the memory footprint of the column index array of...

gmblock Clusters built out of commodity components are becoming more and more prevalent in the supercomputing sector as a cost effective solution for building high...

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Concept hierarchies greatly help in the organization and reuse of information. Multidimensional, hierarchy organized data are widely used in a variety of applications...

The Memory Bandwidth aware Userspace Scheduler (MemBUS) Symmetric Multiprocessor (SMPs) are commonly used as the building blocks for scalable clustered systems. Often...

SMT processors Simultaneous Multithreading (SMT) is a hardware technique that allows a conventional superscalar processor to issue instructions from multiple hardware...

For our more recent work on the Sparse Matrix Vector Multiplication check: CSX. Sparse Matrix Vector Multiplication Sparse Matrix Vector Multiplication (SPMV) is...

Speculative Multithreading and TM Speculative Mutltihreading and TM are two programming models that have been proposed in the literature in the last few years. In...

Stencil Computations The main objective of this activity is to optimize stencil computations for Cluster platforms with commodity (e.g. Gbit Ethernet) or sophisticated...

Transactional Memory (TM) Transactional Memory (TM) is a novel programming model for multicore architectures that allows concurrency control over multiple threads...

Research Research Areas Activities/Projects Bibliography Portal Courses Computer Architecture Advanced Computer Architecture Operating Systems...