Title: "Utilizing underlying synchronization mechanisms for efficient support of different programming models". Abstract: Parallel programming is a very intricate, yet increasingly important, task as we have entered the multicore era and more cores are available to the programmer. One of the biggest challenges is the synchronization of the available threads. It needs to be done not only correctly but also efficiently, as otherwise it can become a bottleneck and hurt performance significantly. Throughout the years, many programming models have been proposed with different approaches regarding the way threads are created, synchronized and managed, as well as their role on speeding up the application (symmetric worker threads, helper threads, speculative threads, etc.). At the same time, different hardware synchronization mechanisms have been proposed and/or implemented (e.g. "lock-box" for SMTs, "full-empty bits" for Cray multithreaded architectures, etc.). This talk reviews our work on how to leverage efficiently underlying synchronization mechanisms for different programming models. More specifically, we will review our earlier work on utilizing the MONITOR/MWAIT instructions (introduced with Prescott core) to synchronize asymmetric threads executing on Intel's Hyper-Threaded processors. Then, we will present our current work on combining the newest synchronization mechanism (Transactional Memory) with helper threads that speculatively exploit optimistic parallelism. This technique has been developed and applied for accelerating Dijkstra's algorithm, a known inherently serial application. Bio: Nikos Anastopoulos received his Diploma in Computer Engineering & Informatics from the Computer Engineering & Informatics Department of the University of Patras, Greece. He is currently a PhD candidate in the School of Electrical and Computer Engineering, National Technical University of Athens. His research interests include parallel and high performance computer architectures, multithreaded and multicore processors, programming models and software techniques for the efficient interaction of scientific applications with emerging multiprocessor architectures. He is a student member of the IEEE.