Difference: StencilComputations (4 vs. 5)

Revision 52008-03-11 - VangelisKoukis

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META TOPICPARENT name="ActivitiesProjects"

Stencil Computations

The main objective of this activity is to optimize stencil computations for Cluster platforms with commodity (e.g. Gbit Ethernet) or sophisticated (e.g. SCI, Myrinet) interconnects. In this context, our research has focused on applying the tiling (or supernode) loop transformation to stencils in order to minimize the communication latency effect on the total parallel execution time of the algorithms. Tiling method groups neighboring computation points of the nested loop into blocks called tiles or supernodes thus increasing the computation grain and decreasing both the communication volume and frequence. Within the domain of stencil computations, nested loops and tiling transformation, our group has coped with several problems. Efficient scheduling techniques of tiled stencil applications that enable communication to computation overlap have been investigated, presented and awarded as one of the four best papers in IPDPS'01 (pdf). Automatic parallelization and efficient code generation methods have been proposed in TPDS (pdf) and Parallel Computing (pdf). Hybrid (MPI + OpenMP) parallel implementations of tiled stencil computations have been presented in IJCSE (pdf).

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